As semiconductor technology advances, more and more functionality is provided within a single integrated circuit. This phenomenon exists not only for processors, controllers and other such devices, but also for so-called system on chip (SoC) devices. Such systems on chip include many different components including one or more internal processors or cores, controllers, interface circuitry, memories and so forth, such that the single integrated circuit acts as an entire embedded system.
Due to the large number of intellectual property (IP) blocks, with a diverse array of input/output ports and potentially several communication fabrics connecting everything together, the level of debug and validation capability must match this increase in complexity. There are a number of techniques available to enable the required level of debug and testing. However, one common technique uses an on-die logic analyzer (ODLA). With current debugging of SoC's whether by ODLA or other means, it can be difficult to match the debug needs with increasing design complexity. For example, buried interconnects are traditionally exposed to a set of re-usable functional package pins through a multiplexing structure. However, finding suitable package pins to re-use is becoming increasingly difficult and the fixed bandwidth of the port limits efficiency and throughput of the overall solution.